1. Field of the Invention
This disclosure relates to a non-volatile semiconductor memory device, and more particularly, to a wordline decoder of a non-volatile semiconductor memory device.
2. Description of the Related Art
In general, semiconductor memory devices are divided into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Volatile semiconductor memory devices are divided into dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. Volatile semiconductor memory devices can perform a read or write operation at a high speed but may lose all data stored in memory cells when an external power supply is turned off. Non-volatile semiconductor memory devices are divided into mask read only memory (MROM) devices, programmable read only memory (PROM) devices, erasable programmable read only memory (EPROM) devices, and electrically erasable programmable read only memory (EEPROM) devices.
Non-volatile semiconductor memory devices can permanently store data in memory cells regardless of whether an external power supply is turned off. As a result, non-volatile semiconductor memory devices are generally used for preserving data independent of a power interruption. However, it is not easy for ordinary users to erase data from or reprogram MROMs, PROMs and EPROMs. EEPROMs are electrically erasable or writable and thus are increasingly used for system program storage devices or auxiliary storage devices for storing data that may need to be updated often.
Flash memory devices, which are one type of EEPROM devices, are programmed by injecting hot electrons from a channel adjacent to a drain region into a floating gate. Specifically, when programming a flash memory device, a source region and a substrate region are grounded, a high voltage of about 9 V is applied to a control gate while a sufficient voltage to generate hot electrons, e.g., a voltage of about 5 V, is applied to a drain region. The threshold voltage of a memory cell programmed in the above-described manner increases because of negative electrons accumulating in a floating gate. When erasing data from a flash memory device, a negative voltage of about −9 V is applied to a control gate, and a voltage of about 9 V is applied to a bulk region so that negative electrons accumulated in a floating gate can be discharged to the bulk region. This effect may be referred to as Fouler-Nordheim Tunneling. Therefore, the threshold voltage of a memory cell erased in the above-described manner becomes lower than before. Programmed memory cells are referred to as off-cells, and erased memory cells are referred to as on-cells.
When reading data from a flash memory device, a voltage of about 1 V is applied to a drain region, and a voltage of 0 V is applied to a source region. A voltage (hereinafter referred to as a read voltage) which is between the threshold voltage of programmed memory cells and the threshold voltage of erased memory cells must be applied to a wordline connected to the memory cell to be read.
NAND-type flash memory devices have a structure in which a memory cell array includes memory strings. Each memory string is formed of multiple memory cells coupled in series, and is itself coupled in series between a bitline and a source line.
FIG. 1 is a circuit diagram of a conventional flash memory device 100. Referring to FIG. 1, the flash memory device 100 includes a block memory cell array 110 and a wordline decoding unit 120. The flash memory device 100 may include multiple block memory cell arrays and respective wordline decoders. For the convenience of description, the flash memory device 100 is illustrated in FIG. 1 with only one block memory cell array 110 and a wordline decoding unit 120 corresponding to the block memory cell array 110.
The block memory cell array 110 includes memory strings CS connected to corresponding bitlines (BL0, BL1, . . . , BLn−1). The memory strings CS are connected to a common source line CSL. Memory cells M0 through M15 of each of the memory strings CS are connected to respective corresponding wordlines WL0 through WL15. The gates string selection transistors SST which connect the memory strings CS to the bitlines BL0 through BLn−1 are connected to a string selection line SSL. The gates of ground selection transistors GST which connect the memory strings CS to the common source line CSL are connected to a ground selection line GSL.
The wordline decoding unit 120 selectively activates the string selection line SSL, the ground selection line GSL, and the wordlines WL0 through WL15. The wordline decoding unit 120 includes a decoder 122 which receives address signals ADDR and generates a block wordline driving signal BLKWL, wordline driving signals S0 through S15, a string selection voltage VSSL, and a ground selection voltage VGSL. The wordline decoding unit 120 also includes a wordline driver 124 which transmits the wordline driving signals S0 through S15, the string selection voltage VSSL, and the ground selection voltage VGSL to the wordlines WL0 through WL15, the string selection line SSL, and the ground selection line GSL, respectively.
The decoder 122 decodes the address signals ADDR and provides a driving voltage to the string selection line SSL, the wordlines WL0 through WL15, and the ground selection line GSL in a program operation, an erase operation, or a read operation. The driving voltage provided by the decoder 122 may be a program voltage Vpgm for a program operation, an erase voltage Verase for an erase operation, or a read voltage Vread for a read operation. In addition, the decoder 122 provides a high voltage VPP to the block wordline driving signal BLKWL.
The wordline driver 124 includes a plurality of high-voltage path transistors SN, WN0 through WN15, GN, and CN. The gates of the high-voltage path transistors SN, WN0 through WN15, GN, and CN are connected to one another and to the block wordline driving signal BLKWL.
In general, the decoder 122 uses a high-voltage N-type MOS (HVNMOS) transistor. An HVNMOS transistor has a higher breakdown voltage, e.g., a breakdown voltage of 25-30 V, than typical N-type MOS transistors having a breakdown voltage of 5-6 V. However, a decoder using HVNMOS transistors requires a considerable number of control signals for applying a voltage to a wordline, and thus, it is difficult to control a decoder using a HVNMOS transistor.
In order to solve the problems with a decoder using a HVNMOS transistor, a method to design a decoder 122 using HPMOS has been developed.
FIG. 2 is a detailed circuit diagram of a decoder 122 using HPMOS, which generates a block wordline driving signal BLKWL. Referring to FIG. 2, the decoder 122 provides a high voltage VPP to the block wordline driving signal BLKWL in response to a block selection signal BLKi. The block selection signal BLKi is generated by decoding input address signals ADDR and is used for selecting a block memory cell array 110.
The block selection signal BLKi is input to a first inverter 201. An output of the first inverter 201 is input to a second inverter 202. An output of the second inverter 202 passes through an NMOS transistor 203 and a first depletion transistor 204 and then is output as the block wordline driving signal BLKWL. The gates of the NMOS transistor 203 and the first depletion transistor 204 are connected to a power supply voltage VDD. The first and second inverters are driven at the power supply voltage VDD.
The decoder 122 includes a second depletion transistor 205 and a PMOS transistor 206 coupled in series between the high voltage VPP and the block wordline driving signal BLKWL. The gate of the second depletion transistor 205 is connected to the block wordline driving signal BLKWL, and the gate of the PMOS transistor 206 is connected to the output of the first inverter 201.
When the level of the power supply voltage VDD decreases to 1.8 V, the decoder 122 generates an undesired current path A increasing the power consumption of a wordline decoder.
It is assumed that the first and second depletion transistors 204 and 205 have a threshold voltage Vth of about −2.2V and the high voltage VPP is between the range of 20V and 25V. Then, when the block selection signal BLKi is logic low, the output of the first inverter 201 is logic high, and the output of the second inverter 202 is logic low. Thus, a block wordline driving signal BLKWL having a logic low level is output via the NMOS transistor 203 and the first depletion transistor 204.
Here, the PMOS transistor 206 should be turned off due to the logic-high output of the first inverter 201. However, since the level of the power supply voltage VDD has decreased, the voltage of a high level on the output of the first inverter 201 has decreased. As a result, the PMOS transistor 206 is turned on.
When the level of the power supply voltage VDD is low and a block wordline driving signal BLKWL having the level of a ground is generated, a direct current (DC) path A passing through the second depletion transistor 205, the PMOS transistor 206, the first depletion transistor 204, the NMOS transistor 203, and an NMOS transistor (not shown) of the second inverter 202 is generated between the high voltage VPP and the ground. Due to the DC path A, the power consumption of a wordline decoder increases.
Therefore, in order to reduce the power consumption of the decoder 122, it is necessary to develop a wordline decoder capable of preventing an undesired current path from being generated even at lower power supply voltage levels.